1. Field of the Invention
This invention relates to integrated circuit (IC) packaging. In particular, the invention relates to multi-layered organic land grid array (OLGA).
2. Description of Related Art
As demand for high performance integrated circuits (IC's) grow, IC packaging becomes more and more important. Once an IC has been fabricated, it is placed inside an IC package. The circuits within the IC are electrically and mechanically coupled to interconnects to leads on the external surface of the package. An IC package not only protects the IC from damage but also provides power, interconnections for input/output (I/O), and heat removal. The considerations for a suitable operating environment includes signal propagation delays. The propagation delays are affected by the overall inductance. In the manufacture of IC packaging, especially for high performance processors, there are two competing requirements: wiring densities and low inductance. It is desirable to achieve greatest wiring densities while at the same time forming interconnections between adjacent layers that provide as low inductance as possible. The formation of high quality via holes, or vias, that are used for interconnections, is an important step in forming high quality interconnections.
The requirements for suitable operating environment due to the complexity of modern processors lead to the introduction of a number of packing technologies. Among these new packaging technologies, grid array packaging has become more and more popular. Examples of these grid array packaging includes pin grid array (PGA), ball grid array (BGA), and land grid array (LGA).
The LGA is essentially a leadless package having dense connection pads in a pitch matrix array, which reduces propagation delays and other environmental effects. There are two types of LGA: plastic LGA (PLGA) and organic LGA (OLGA). The OLGA includes organic material mixed with copper which provides better thermal expansion than the PLGA and is suitable for high density and high performance microprocessors. To accommodate the complexity of modern processors, the circuitry is typically packaged in a multi-layer configuration where a number of layers is placement of circuit elements. A multi-layer package provides a small footprint for the resulting device and reduce propagation delays due to short interconnection lengths. However, a multi-layer design also presents difficulties in formation of vias.
In designing a multi-layer OLGA package, vertical connections between layers are implemented using staggered vias. A staggered vias design is preferred to a stacked vias design because stacked vias are not manufacturable for OLGA.
FIG. 1 shows a prior art spiral via design 100 in a cross-sectional view on the XZ plane and a top view in the XY plane. For illustration purposes, eight layers are shown. There are no metal layers on the top and bottom layers. Vias are connected to a C4 bump and the BGA balls directly.
The cross-sectional view in the XZ plane shows vertical connections 110, 120, 130, 140, 150, 160 and 170, connecting to layers 115, 125, 135, 145, 155, and 165, respectively. Vias are referenced by referring to the corresponding vertical connections. In this spiral design, the vias are laid out around a center and formed a three-dimensional spiraled structure. For example, the vias corresponding to the vertical connection 140 are at the center and the vias corresponding to vertical connections 110, 120, 130, 150, 160, and 170 are laid around it.
FIG. 2 shows another prior art stretched via design 200 in a cross-sectional view on the XZ plane and a top view in the XY plane. For illustration purposes, eight layers are shown. Again there are no top and bottom layer metal connections and vias are connected directly to the C4 bump and BGA balls directly.
The cross-sectional view in the XZ plane shows vertical connections 210, 220, 230, 240, 250, 260 and 270, connecting to layers 215, 225, 235, 245, 255, and 265, respectively. Vias are referenced by referring to the corresponding vertical connections. In this stretched design, vias are restricted in the Y=0 plane and are placed along the X direction while moving to upper layers. For example, the vias corresponding to the vertical connections 270, 260, 250, 240, 230, 220, and 210 are arranged in a somewhat linear fashion moving through the layers 265, 255, 245, 235, 225, and 215 in a staircase or stretched fashion. This stretched via design has a maximum travel distance along the X direction.
Both the spiral and stretched designs shown in FIGS. 1 and 2 suffer a major drawback. The total inductance of both via design is large because most of the mutual inductances between adjacent layers are additive to the total inductance. The large total inductance reduces signal integrity in the signal paths.
Therefore there is a need to provide an efficient technique to provide a via design for the OLGA with minimum total via inductance.